There are several approaches we can take to achieve this based on the higher performance of the logic. For example, we can run AXI buses narrower but at a higher frequency; in this case we leverage the increased performance of the fabric. This works well for interfaces around our module, although the core of the module may require different techniques.

These approaches may be necessary to maintain the throughput of a processing core or the dynamic range of a filter, for example.

One technique that can be used in processing cores and filters is RAM pumping.

If you are not familiar with RAM pumping, it involves running the BRAM at multiples of the clock frequency used to clock the rest of the processing core.

In the simplest implementation this might mean running the BRAM at double the rate; in others, we could run the clock faster, perhaps four times the processing-chain clock. The exact choice depends on the needs of the processing chain, the available clock rates, and of course the performance of the selected device.

If we are implementing BRAM pumping, we must ensure that the clocks are related to each other and are integer multiples.

The diagram below shows an example of the simplest double-pumping scheme, which performs one read and one write during a single clock cycle of the processing chain.

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